Ravi Kukreti's Résumé
Author
ravi kukreti
Last Updated
4年前
License
Creative Commons CC BY 4.0
Abstract
Ravi Kukreti's résumé. Created with the Deedy CV template.
Ravi Kukreti's résumé. Created with the Deedy CV template.
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% TITLE SECTION
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\namesection{RAVI} {KUKRETI}{ % Your name
\href{mailto:dd367@cornell.edu}{ravik.ev.17@nsit.net.in} | 7906305118 % Your contact information
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\begin{minipage}[t]{0.33\textwidth} % The left column takes up 33% of the text width of the page
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% Education
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\section{Education}
\subsection{NSIT (DELHI UNIVERSITY)}
\descript{M.tech in Embedded and VLSI}
\location{Dwarka, New Delhi \\ Cum. GPA: 7.67}
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\subsection{GRAPHIC ERA UNIVERSITY}
\descript{B.tech in ECE}
\location{Dehradun | Cum. GPA: 7.4}
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\subsection{ARMY SCHOOL DEHRADUN}
\descript{HSC}
\location{CLEMENTTOWN | PERCENTAGE: 71}
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\subsection{ARMY SCHOOL DEHRADUN}
\descript{SSC}
\location{CLEMENTTOWN | PERCENTAGE: 73.2}
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% Coursework
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\section{Coursework}
\subsection{Graduate}
Digital Integrated Circuit \\
Semiconductor Devices and Memories \\
Analog Integrated Circuit \\
STA(udemy course) \\
Processor Design \\
Device Modelling and Circuit simulation
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% Skills
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\section{Skills}
\subsection{Programming}
Verilog \\
SystemVerilog \\
C basics \\
TCL (CLI)
\subsection{TOOL}
Vim \\
Eldo(Mentor Graphics) \\
LT- spice \\
Xillinx \\
Questa Sim
\sectionspace % Some whitespace after the section
\section{ACHIEVEMENTS}
IEEE Conference resarch paper on Implementation of Probability Using FIR filter.(2014) \\
IEEE resarch paper on Performance Optimization of Digital CMOS logic circuits using LE theory and APSO.(2019) \\
GATE Percentile 98.67(2016) \\
GATE Percentile 98.53(2018)
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% Experience
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\section{Experience}
\runsubsection{TRUECHIP SOLUTIONS}
\descript{| Training}
\location{ Jan 2019 – Apr 2019 | Noida, UP}
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\begin{tightitemize}
\item Deep learning of hardware descriptive and verification language using Verilog and SystemVerilog. understanding of verification environment using UVM methodology.
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\section{PROJECT}
\runsubsection{DESIGN AND VERIFICATION OF 8b9b ENCODER}
\location{May 2019 – July 2019 | Noida, UP}
\begin{tightitemize}
\item Encoding 8bit into 9bit and writing DUT using SystemVerilog.
\item A verification environment is created using UVM methodology to verify the correct functionality of DUT.
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\runsubsection{OPTIMUM TRANSISTOR SIZING OF CMOS LOGIC CIRCUIT USING LE THEORY AND APSO ALGORITHM}
\location{Jan 2019 – Apr 2019 | Dwarka, New Delhi}
\begin{tightitemize}
\item Using LE theory transistor Delays are optimized and with the help of nature inspired algorithm i.e APSO iteration on transistor size provide minimum area and power, hence improved PDAP.
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\runsubsection{PROGRAMMABLE CIRCUIT USING MEMRISTOR}
\location{Aug 2018 – Dec 2018 | Dwarka, New Delhi}
\begin{tightitemize}
\item Memristors are used to develop oscillator circuits, RC phase shift oscillator, Comparator circuit.
\item With the help of triggering pulse memristor are used as memory devices storing logical bit values.
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\runsubsection{DESIGN AND IMPLEMENTATION OF 8BIT RISC PROCESSOR}
\location{Sep 2017 – Nov 2017 | Dwarka, New Delhi}
\begin{tightitemize}
\item Implementation of various unit such as control unit, data path unit and memory unit with the help of Verilog HDL.
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% Research
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\section{Research}
\runsubsection{VLSI design Lab}
\descript{| Head Postgrad Research}
\location{Jan 2019 – Apr 2019 | Dwarka, New Delhi}
Worked with \textbf{\href{http://www.cs.cornell.edu/~asaxena/}{Dr. Kunwar Singh}}
\begin{tightitemize}
\item Automation of CMOS transistor sizing and improving PDAP.
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% Awards
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\section{POSITION OF RESPONSIBILITY}
\runsubsection{NSIT- NEW DELHI}
\descript{| TEACHING ASSISTANTSHIP}
\location{Aug 2017 – Apr 2019 | Dwarka, New Delhi}
Teaching Assistantship in Embedded and VLSI labs.
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